The present invention pertains to methods for forming a metal diffusion barrier on a partially fabricated integrated circuit. The methods employ at least one operation that selectively etches barrier material from the bottom of vias while simultaneously depositing barrier material on most regions of the integrated circuit. The methods are frequently performed on unlanded vias.
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for integrated circuits. While copper has a greater conductivity than aluminum, it has not been used because of certain challenges it presents, including the fact that it readily diffuses into silicon oxide and degrades insulating electrical properties even at very low concentrations. Recently, however, IC manufacturers have been turning to copper because of its high conductivity and electromigration resistance, among other desirable properties. Most notable among the IC metalization processes that use copper is Damascene processing. Damascene processing is often a preferred method because it requires fewer processing steps than other methods and offers a higher yield. It is also particularly well suited to metals such as Cu that cannot readily be patterned by plasma etching.
Damascene processing is a method for forming interconnections on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). In order to frame the context of this invention, a brief description of a copper dual Damascene process for forming a partially fabricated integrated circuit is described below. Note that the invention applies to other fabrication processes including single Damascene processes.
Presented in FIGS. 1A-1F, is a cross sectional depiction device structures created at various stages of a dual Damascene fabrication process. A cross sectional depiction of a completed structure created by the dual Damascene process is shown in FIG. 2. Referring to FIG. 1A, an example of a typical substrate, 100, used for dual Damascene fabrication is illustrated. Substrate 100 includes a pre-formed dielectric layer 103 (such as fluorine or carbon doped silicon dioxide or organic-containing low-k materials) with etched line paths (trenches and vias) in which a diffusion barrier 105 has been deposited followed by inlaying with copper conductive routes 107. Because copper or other mobile conductive material provides the conductive paths of the semiconductor wafer, the underlying silicon devices must be protected from metal ions (e.g., Cu2+) that might otherwise diffuse or drift into the silicon. Suitable materials for diffusion barrier 105 include tantalum, tantalum nitride, tungsten, titanium tungsten, titanium nitride, tungsten nitride, and the like. In a typical process, barrier 105 is formed by a physical vapor deposition (PVD) process such as sputtering, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Typical metals for the conductive routes are aluminum and copper. More frequently, copper serves as the metal in Damascene processes, as depicted in these figures. The resultant partially fabricated integrated circuit 100 is a representative substrate for subsequent Damascene processing, as depicted in FIGS. 1B-1F.
As depicted in FIG. 1B, a silicon nitride or silicon carbide diffusion barrier 109 is deposited to encapsulate conductive routes 107. Next, a first dielectric layer, 111, of a dual Damascene dielectric structure is deposited on diffusion barrier 109. This is followed by deposition of an etch-stop layer 113 (typically composed of silicon nitride or silicon carbide) on the first dielectric layer 111.
The process follows, as depicted in FIG. 1C, where a second dielectric layer 115 of the dual Damascene dielectric structure is deposited in a similar manner to the first dielectric layer 111, onto etch-stop layer 113. Deposition of an antireflective layer 117, typically a silicon oxynitride, follows.
The dual Damascene process continues, as depicted in FIGS. 1D-1E, with etching of vias and trenches in the first and second dielectric layers. First, vias 119 are etched through antireflective layer 117 and the second dielectric layer 115. Standard lithography techniques are used to etch a pattern of these vias. The etching of vias 119 is controlled such that etch-stop layer 113 is not penetrated. As depicted in FIG. 1E, in a subsequent lithography process, antireflective layer 117 is removed and trenches 121 are etched in the second dielectric layer 115; vias 119 are propagated through etch-stop layer 113, first dielectric layer 111, and diffusion barrier 109.
Next, as depicted in FIG. 1F, these newly formed vias and trenches are, as described above, coated with a diffusion barrier 123. As mentioned above, barrier 123 is made of tantalum, or other materials that effectively block diffusion of copper atoms into the dielectric layers.
After diffusion barrier 123 is deposited, a seed layer of copper is applied (typically a PVD process) to enable subsequent electrofilling of the features with copper inlay. FIG. 2 shows the completed dual Damascene process, in which copper conductive routes 125 are inlayed (seed layer not depicted) into the via and trench surfaces over barrier 123.
Copper routes 125 and 107 are now in electrical contact and form conductive pathways, as they are separated only by diffusion barrier 123, which is also somewhat conductive. Traditionally these diffusion barriers are deposited using PVD methods because of the high quality resultant films. However, when depositing in features with higher aspect ratios such as the narrow vias within modern technologies, PVD methods tend to produce films with poor sidewall coverage and thick bottom coverage. To produce films with improved step coverage in vias and trenches, CVD and ALD methods are being considered. However, the bulk resistivity of film using CVD and ALD methods tend to be high, resulting in a high via resistance or poor resistance distribution. Therefore, the common issue to using each of these methods is a high via resistance. In the case of CVD or ALD, it is due to the high bulk resistivity of the film (i.e.  greater than 1000 xcexcxcexa9 cm). In the case of PVD, it is due to high bottom coverage.
Thus, to reduce resistance between the copper routes, a portion of the diffusion barrier may be etched away, specifically at the via bottom, in order to expose the lower copper plug. This approach is generally described in U.S. Pat. No. 6,287,977 to Hashim et al., U.S. Pat. No. 5,985,762 to Geffken et al., and U.S. patent application Ser. No. 09/965,472 filed Sep. 26, 2001, incorporated by reference above. By completely etching away the barrier in the via bottom, the subsequent copper inlay can be deposited directly onto the lower copper line. Conventional methods for etching away diffusion barriers at the bottom of vias (for example, the region of barrier 127 contacting copper inlay 107 in FIG. 1F) are problematic in that they are not selective enough. That is, conventional etch methods remove barrier material from undesired areas as well, such as the corners (edges) of the via, trench, and field regions. This can destroy critical dimensions of the via and trench surfaces (faceting of the corners) and unnecessarily exposes the dielectric to plasma. This may lead to dielectric damage, such as critical dimension loss, increase in dielectric constant (with concomitant negative impact on device speed), and poor adhesion to the barrier layer. These problems will be encountered with the method described in the Geffken et al. patent.
Further, when etching through barrier layers and into the underlying copper metal, some copper oxide and etch residues (including polymeric etch residues) are sputtered onto the barrier sidewall. In the unlanded via case, dielectric material is sputtered along with the underlying copper metal onto the barrier side wall. Subsequently, when a copper seed layer is deposited, it forms directly on these contaminants. As a consequence, the copper seed layer may exhibit a myriad of problems, including poor adhesion, seed discontinuity, fill voiding, etc. Each of these problems negatively impact device performance, yield, and reliability. Such issues are expected with the method described in the Hashim et al. patent.
In addition, conventional etching methods do not address xe2x80x9cunlandedxe2x80x9d via regions typical of modem devices. In some cases these unlanded vias do not fully overlap with the underlying copper inlay 107. Such unlanded via is illustrated in FIG. 1F wherein a portion of diffusion barrier 123 is located at via bottom 127. In the unlanded via case, a portion of the barrier rests on copper inlay 107 and a portion rests on dielectric 103. A conventional barrier etch, meant to expose copper inlay 107, would expose both copper inlay 107 and dielectric 103 in region 127. If copper were to be deposited on such structure, it could diffuse directly into dielectric 103 through region 127. The Hashim et al. patent mentioned above does not also address this problem.
What are therefore needed are improved methods of forming diffusion barriers on integrated circuit structures, selective methods in which the diffusion barrier thickness is minimized at the bottoms of vias without sacrificing the integrity of the diffusion barrier in other regions. Preferably, this is accomplished in a manner that accounts for the special considerations of unlanded vias.
The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit. It provides a continuous, relatively thin barrier coverage at via bottoms for good reliability (even when unlanded vias are used) and low via resistance. The invention also provides a sufficiently thick barrier coverage on via sidewalls to address reliability issues such as stress migration and electromigration resistance. By selectively etching at the via bottoms, and not necessarily elsewhere, the invention also minimizes corner xe2x80x9cblow-outxe2x80x9d and faceting of vias without changing in feature critical dimensions. Still further, the invention minimizes copper contamination during wafer manufacturing processes and preserves properties of inter-level dielectrics by eliminating or minimizing direct plasma exposure. In general, methods of this invention lower wafer manufacturing costs by increasing yield.
The present invention pertains to various methods for forming a diffusion barrier. When integrated with a seed layer deposition operation, the method typically includes at least four operations. The first operation deposits barrier material via PVD, CVD or ALD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. In cases in which unlanded vias may exist (and in some instances in which unlanded vias do not exist), a third operation is performed wherein at least a small amount of a barrier material is deposited over at least the bottoms of the vias to protect the dielectric material of the previous interconnect layer. The third operation uses at least one of PVD, CVD or ALD techniques. Typically, the barrier material deposited in the third operation covers at least the lower sidewalls of the vias (in addition to the via bottoms) and provides a high quality template on which to deposit a subsequent metal conductive layer. In some embodiments, at least part of the second operation is performed in the same processing chamber as the third operation. The forth operation deposits a metal conductive layer over the substrate to form a conductive route to the next metalization layer. In preferred embodiments of the invention, all four operations are done in a single process tool without breaking vacuum. In some embodiments, an additional operation is performed between the third and forth operation. This operation deposits another portion of barrier material and simultaneously etches a portion of the barrier material deposited in the third operation.
In preferred embodiments of the invention, a degas operation is performed prior to the first operation. The purpose of the degas operation is to remove unwanted moisture and hydrocarbon etch residue that may exist on the wafer. The degas operation can be performed by heating the wafer to between about 200 to 400 degrees Celsius, for example, depending on the type of dielectric and other materials in the device.
The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the sidewalls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In a preferred embodiment of the invention, selective etching is also used to remove contaminants under the barrier material, thus obviating a separate preclean operation before the first operation. In alternative embodiments, the preclean operation is performed before the first operation.
The invention accomplishes simultaneous etch and deposition by creation of defined plasma producing process conditions such that barrier material is etched away in some regions while in other regions diffusion barrier material is deposited. This is the second of the four operations described previously. The descriptive term xe2x80x9cetch to deposition ratioxe2x80x9d or xe2x80x9cE/Dxe2x80x9d is used herein to characterize process conditions at any position on substrate. More specifically, in the context of a partially fabricated integrated circuit having via and trench surface features, methods described herein provide that E/D varies as a function of the elevation profile of the surface features to which the plasma is applied. Generally, E/D is greatest at the bottommost regions of the wafer surface features and decreases in magnitude as elevation increases. At a position where there is no net gain or loss of material, the etch and deposition processes equal each other and the E/D is 1. So preferably, the E/D is greater than 1 at the via bottom, but may be less than 1 on the trench step and on the field region.
A preferred diffusion barrier material for this etch/deposition sputter is tantalum, although the invention is not limited to tantalum. Other materials for which the invention is applicable include but are not limited to tungsten, cobalt, solid solutions (interstitial forms) of tantalum and nitrogen and binary nitrides (e.g. TaNx, TiN, WNx). After diffusion barriers of the invention arc formed, a metal conductive layer is deposited thereon.
Preferably methods of the invention are used in Damascene processing in which the metal conductive layer and interconnects are made of copper. In some preferred methods of the invention, the metal conductive layer is a copper seed layer. Preferably seed layers of the invention are formed using PVD, but the invention is not limited in this way. As mentioned, in some methods of the invention, all aspects of a process flow for forming a diffusion barrier and depositing a metal conductive route thereon are done in the same processing tool. While a preferred conductive metal material for this deposition is copper, the invention is not limited to copper. Other materials for which the invention is applicable include aluminum and conductive alloys of aluminum or copper.
Methods of the invention create diffusion barriers having stack structures. Distinct portions of each stack may be deposited (layered) using PVD, CVD, ALD or other methods. Thus diffusion barriers of the invention may have monolayered, bilayered, trilayered or multilayered structures. Preferably, the portions include at least one of tantalum, nitrogen-doped tantalum, tantalum nitride, and titanium silicon nitride. More detail of preferred arrangements for the layering of these materials, methods of depositing, and structure of the diffusion barriers formed therefrom, will be described in the detailed description below.
Methods of the invention create diffusion barriers within integrated circuitry using at least the materials described above. Therefore, another aspect of the invention pertains to an integrated circuit or a partially fabricated integrated circuit. Preferably integrated circuits or partially fabricated integrated circuits of the invention include a diffusion barrier which covers all surfaces of a plurality of vias and a plurality of trenches with minimal diffusion barrier material at the bottom of the plurality of vias, and a metal conductive layer provided thereon, such that the diffusion barrier provides relatively little resistance to electrical conduction between the metal conductive layer and the plurality of metal conductive routes at the bottom of the plurality of vias.
A diffusion barrier which covers all surfaces of a plurality of vias and a plurality of trenches, said diffusion barrier having a thickness of between about 50 and 400 xc3x85 on said surfaces except at the bottom of the plurality of vias where there is less than about 50 xc3x85 of diffusion barrier material; and a metal conductive layer provided thereon.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.